Extreme DA™ announced that Japan’s leading semiconductor research organization, the Semiconductor Technology Academic Research Center (STARC), has confirmed its adoption of the Extreme GoldTime™ timing analyzer. GoldTime is being used for STARC’s statistical static timing analysis (SSTA) flow of STARCAD-CEL (V3.0). STARC has already released this flow to its member companies. GoldTime was first chosen by STARC in 2007 and has been in use at STARC since that date.
Statistical Analysis Software Required for IC Designs at 65-nm and Below
At advanced semiconductor process nodes of 65-nm and below, statistical analysis software is required for analyzing systematic and random variations that affect the performance of IC designs. Variation-aware analysis helps designers understand what the effects these variations have on achieving timing targets for their IC designs.
GoldTime has exceeded STARC’s accuracy requirements for 45-nm and delivers excellent turn-around-times for analysis due to its multi-threaded software architecture. STARC has established the precision of the GoldTime timing analyzer and validated a variation-aware SSTA flow using a range of 45-nm designs. STARC engineers analyzed test chips and confirmed the benefits of the SSTA design flow compared with traditional worst-case corner methods. STARC member companies can expect to reduce turn-around-time, IC die area, and power loss from leakage by employing GoldTime.
“Our member companies have available to them an advanced, variation-aware analysis solution for timing sign-off,” said Nobuyuki Nishiguchi, vice-president and general manager of Development Department-1 at STARC. ” STARCAD-CEL (V3.0) flow using SSTA technology from Extreme DA enhances accuracy and quality of timing analysis, and can take into account signal crosstalk and power-supply noise. STARC members will see reductions in turn-around-time, IC die area, and power leakage.”
“The continuing use by STARC of Extreme GoldTime as a part of its variation-aware SSTA flow is a strong endorsement of the technological leadership of our timing solution,” said Mustafa Celik, president and CEO of Extreme DA. “The speed, accuracy, and capacity of our new-generation analysis tools continue to advance. Our collaboration with STARC has validated new kinds of analysis that will be crucial for makers of advanced IC designs.”
The Semiconductor Technology Academic Research Center, STARC, is a research consortium co-founded by major Japanese semiconductor companies in December 1995. STARC’s mission is to contribute the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies.
About Extreme DA
Headquartered in Santa Clara, Calif., venture-funded Extreme DA develops and licenses software products for the timing sign-off of 65- and 45-nanometer integrated circuits. The company’s investors include Foundation Capital, IT-Farm Corporation, and Lanza techVentures. For the latest news and information on Extreme DA, visit www.extreme-da.com or write to email@example.com.
Extreme DA and GoldTime are trademarks of Extreme DA. All other legal marks are the property of their respective owners.